System PLL Units

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The five system PLLs provide a 750 to 1600 MHz clock to the clock generators. The frequency and jitter specifications for the APLL, DPLL, RPLL, IOPLL, and VPLL system PLLs are in the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].