System Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: APU System Control Registers describes the APU registers.

Table 3-2:      APU System Control Registers

Register name

Overview

ERR_CTRL

Control register

ISR

Interrupt status register

IMR

Interrupt mask register

IEN

Interrupt enable register

IDS

Interrupt disable register

CONFIG_0

CPU core configuration

CONFIG_1

L2 configuration

RVBARADDR{0:3}{L,H}

Reset vector base address

ACE_CTRL

ACE control register

SNOOP_CTRL

Snoop control register

PWRCTL

Power control register

PWRSTAT

Power status register

 

IMPORTANT:   Do not perform a load/store exclusive to the device memory unless a workaround for the Arm® processor Cortex-A53 MPCore (MP030) product errata notice 829070 for APU registers is implemented. Speculative data reads might be performed to device memory.