System Test and Debug Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DAP controller accesses system test and debug functions. It is a CoreSight component of the access and control class, and connects to other components using the programming bus. The DAP controller provides two interfaces to access the CoreSight infrastructure.

External interface using JTAG, from the device pinout.

Internal interface using the APB slave, from the slave interconnect.

A debugger can use JTAG to communicate with the CoreSight infrastructure, while software running on a CPU uses the APB through memory-mapped addresses assigned to the CoreSight infrastructure.

The DAP controller can forward system access requests arriving through either the JTAG or APB slave interfaces to the requested CoreSight components. Also, the DAP controller has an AHB master interface on the LPD AXI interconnect to access system elements in the PS other than the CoreSight components.

The DAP controller can forward system memory requests from the JTAG interface to the other system elements in the PS subject to authentication.

The debug system is spread across three power domains (LPD, FPD, and PLPD). Although all power domains should be turned on for full functionality, the basic JTAG functions work as long as the LPD and PLPD power is present. Power is discussed in Clocks, Reset, and Power Domains.