The System timer can be exclusively configured for A53 and R5F by reading and writing to IOU_SCNTR and IOU_SCNTRS registers residing in the LPD_IOU domain. These registers can be accessed by any master. Both registers IOU_SCNTR and IOU_SCNTRS map to the same physical timer (IOU_SCNTR is read-only). The clock is controlled by the CRL_APB.DBG_TSTMP_CTRL register Vivado PCW [DBG_TSTMP] setting.
For more information refer to the Cortex-R5F or Cortex-A53 MPCore TRMs [Ref 46] [Ref 47].
Register Name |
Address |
Access Type |
Description |
---|---|---|---|
IOU_SCNTR |
0xFF250000 |
Read/Write |
System Timestamp Generator |
IOU_SCNTRS |
0xFF260000 |
Read/Write |
System Timestamp Generator- Secure |