System Trace Macrocell

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

The system trace macrocell (STM) provides software trace instrumentation. The STM (This Figure) provides an APB interface for software and debugger access, and connects to the ATB for trace output, along with authentication inputs, trigger events, and acknowledge.

Figure 39-6:      STM Block Diagram

X-Ref Target - Figure 39-6


The STM supports a trace stream that conforms to the MIPI System Trace Protocol version 2. The STM block is a software application driven trace source to generate an application software instrumentation trace (SWIT). The STM hardware event observation interface enables monitoring and tracing of 64 hardware events, each of which is represented by a single bit. This functionality can be used to monitor interrupts, cross-triggers, and other signals in the system.

STM bits [63:30] are rising edge trigger, where:

63:62 are inverted TRIGOUT[5:4] from cross-trigger interface (CTI)

61:60 are non-inverted TRIGOUT[5:4] from CTI

59:30 are PL events, stm_event[59:30]

STM bits [29:0] are level trigger, where:

29:0 are PL events, stm_event[29:0]

The STM supports the following functions.

printf style debugging.

Trace OS and application events.

Emit diagnostic system information.

Multiple channels for multiple processors to share without conflict with the other.

Trace hardware events.

Trace timestamp with global timestamp.

Generates the MIPI STPv2.

The Arm CoreSight STM-500 System Trace Macrocell Technical Reference Manual, r0p0ARM [Ref 44] contains more details on the STM.

STM can provide support for up to 128 MasterIDs with 64k channels. The 16 MB aligned address space is allocated to the STM instrumentation trace for the channels. All of the MasterIDs overlap to the same 16 MB of address space. The channels are allocated by the software to the MasterID. The STM AXI slave is write-only. The reads to an STM AXI slave always returns OKAY with all-0 data.

The AXI AWADDRS[31:0] is used in the STM as follows:

Bits [31:30] are not used.

Bits [29:24] defines bits [5:0] of MasterID.

Bits [23:8] define the Channel ID.

Bits [7:0] define the address space of a single stimulus port.

The Zynq UltraScale+ MPSoC maps the interconnect AXI to the STM AXI-slave as shown.

STM_AWADDRS[23:0] = AXI_AWADDR[23:0]       //Channels

STM_AWADDRS[29:24] = function of MasterID  //MasterID

The MasterID can be mapped to the STM MasterID as listed in Table: Zynq UltraScale+ MPSoC MasterID Mapped to the STM MasterID.

Table 39-9:      Zynq UltraScale+ MPSoC MasterID Mapped to the STM MasterID

MasterID Indicates




{MasterID[9:6], ACPU<n>}

APU request must be mapped to the STM MasterID.


{MasterID[9:6], RCPU<n>}

AWID needs to be mapped to RPU#



Use the upper 4 bits of the MasterID to uniquely identify the masters.