System Watchdog Timers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are three system watchdog timer (SWDT) units in the PS. They are all based on the Arm system watchdog timer architecture. One major difference between the timers is the system interface signals.

The clock source for the LPD and FPD watchdog timers can come from one of three sources. The CSU_SWDT can source its clock from either the local bus or directly from the PS_REF_CLK pin.

A watchdog timer is used to detect and recover from system malfunctions. The watchdog timer can be used to prevent system lockup; for example, when software becomes trapped in a deadlock. In normal operation, an interrupt handler running on a processor restarts the watchdog timer at regular intervals before the timer counts down to zero. In cases where the timer does reach zero and the watchdog is enabled, one or a combination of the following signals is generated: a system reset, an interrupt, or an external signal. The watchdog timeout period and the duration of any output signals are programmable.

There are three watchdog timers in the system. Each timer has the same programming model and similar control registers.

LPD_SWDT: uses the SWDT register set and is sometimes referred to as swdt0.

FPD_SWDT: uses the WDT register set and is sometimes referred to as swdt1.

CSU_SWDT: uses the CSU_WDT register set.

The LPD watchdog timer, LPD_SWDT, protects the RPU MPCore and its interconnect. The FPD watchdog timer, FPD_SWDT, protects the APU MPCore and its interconnect. The third watchdog timer, CSU_SWDT, protects the CSU and PMU interconnects. It also includes a logic built-in self-test (LBIST) to promote operating safety.

The APU SWDT can be used to reset the APU or the FPD. The RPU SWDT can be used to reset the RPU or the LPD.

An internal 24-bit counter.

Variable timeout period, from 1 ms to 30 seconds using a 100 MHz clock.

Programmable reset period.

This Figure is a block diagram of the watchdog timer.

Figure 14-3:      SWDT Block Diagram

X-Ref Target - Figure 14-3

X17917-system-watchdog-timer-block.jpg

This Figure notes:

Clock selects: FPD_SLCR.WDT_CLK_SEL [select] and FPD_SLCR.WDT_CLK_SEL [select].

MIO pin selects: IOU_SLCR.MIO_PIN_x registers.

Program the clock prescaler and restart values: {SWDT, WDT, SU_WDT}.CONTROL [CLKSEL], [CRV].

A restart signal causes the 24-bit counter to reload the [CRV] value and restart counting.

A halt signal causes the counter to halt during CPU debug (same behavior as the APU SWDT).

The halt conditions are as follows:

°Clock selects: FPD_SLCR.WDT_CLK_SEL [select] and FPD_SLCR.WDT_CLK_SEL [select].

°LPD system WDT– halted by RPU only; either core in the debug can halt it.

°LPD CSU WDT– halted by RPU only; either core in the debug can halt it.

°FPD System WDT– halted by APU only; any core in the debug can halt it.