System-level Control Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The system-level control register sets are used to control the PS behavior. The detailed descriptions for each register is available in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4]. A summary of the registers with their base addresses is shown in Table: System-level Register Sets. Several register sets always require a secure access. All registers are accessed via the XPPU, which can set the access requirements for secure, read/write, and by master. For more information on System Software Mutexes ,see System Software Mutexes on Zynq UltraScale [Ref 59].

Table 10-4:      System-level Register Sets

Base Address

Name

Secure Access

Description

0xFD1A_0000

CRF_APB

XMPU

FPD clock and reset control.

0xFD5C_0000

APU

XMPU

APU control. See Table: APU System Control Registers.

0xFD61_0000

FPD_SLCR

XMPU

Global SLCR for full-power domain (FPD).

0xFD69_0000

FPD_SLCR_SECURE

Yes

Global SLCR for FPD TrustZone settings for PCIe, SATA, and other protocols.

0xFF18_0000

IOU_SLCR

XPPU

IOU SLCR for MIO pin configuration.

0xFF24_0000

IOU_SECURE_SLCR

Yes

IOU SLCR for AXI read/write protection configuration.

0xFF26_0000   

IOU_SCNTRS   

Yes

Always    system timestamp generator.

0xFF41_0000

LPD_SLCR

XPPU

SLCR for the low-power domain (LPD).

0xFF4B_0000

LPD_SLCR_SECURE

Yes

SLCR for LPD TrustZone configuration.

0xFF5E_0000

CRL_APB

XPPU

LPD clock and reset control.

0xFF9A_0000

RPU

XPPU

RPU control.

0xFD6E_0000

CCI_GPV

Yes

CCI_GPV (CCI400, parameters)

0xFD70_0000

FPD_GPV

Yes

FPD_GPV (parameters)