System-level Software Reset

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each module in the PS has one or more software controlled resets that are asserted from the reset module to the PS block residing in the low-power or full-power domain. The resets are generated by the reset module that is in the same power domain as the consuming module. For instance, the APU resets come from the reset block in the FPD, while the Cortex®-R5F resets come from the reset block in the LPD. The reset block in the LPD is reset when there is a system-level reset. A reset applied to the reset block in the FPD resets all the blocks in the FPD.

Software can write to the FPD reset pin in register APB_CRL.RST_LPD_TOP [FPD_RESET] to reset the FPD logic. The PMU also has the ability to reset the FPD.

The WARMRSTREQ signal from the APU is routed to the PMU. It can be used to trigger a block reset to the APU system.

 

IMPORTANT:   The system can hang when software reset control is asserted during a pending AXI/APB transfer.

Table: Resets to System Elements summarizes the block-level reset register for each of the blocks in the LPD and FPD.

Table 38-3:      Resets to System Elements

System Element

Register

Description

LPD System Elements (CRL_APB Register Set)

GEM

RST_LPD_IOU0[gem<0-3>_reset]

GEM Ethernet controllers.

GPIO

RST_LPD_IOU2[gpio_reset]

GPIO controller.

LPD DMA

RST_LPD_IOU2[lpd_dma_reset]

LPD DMA controller.

NAND

RST_LPD_IOU2[nand_reset]

NAND controller.

LPD SWDT

RST_LPD_IOU2[swdt_reset]

LPD watchdog timer (wdt1).

TTC

RST_LPD_IOU2[ttc{0:3}_reset]

TTC triple counter.

I2C

RST_LPD_IOU2[i2c{0:1}_reset]

I2C controller.

CAN

RST_LPD_IOU2[can{0:1}_reset]

CAN controller.

SDIO

RST_LPD_IOU2[sdio{0:1}_reset]

SDIO controller.

SPI

RST_LPD_IOU2[spi{0:1}_reset]

SPI controller.

UART

RST_LPD_IOU2[uart{0:1}_reset]

UART controller.

QSPI

RST_LPD_IOU2[qspi_reset]

Quad-SPI controller.

PS SYSMON

RST_LPD_TOP[sysmon_reset]

PS system monitor.

RTC

RST_LPD_TOP[rtc_reset]

Real-time clock.

APM

RST_LPD_TOP[apm_reset]

AXI performance monitor.

IPI

RST_LPD_TOP[ipi_reset]

Interprocessor interrupts (IPI).

USB

RST_LPD_TOP[usb{0:1}_apb_reset]

RST_LPD_TOP[usb{0:1}_hiberreset]

RST_LPD_TOP[usb{0:1}_corereset]

USB controller.

RPU

RST_LPD_TOP[rpu_pge_reset]

RST_LPD_TOP[rpu_amba_reset]

RST_LPD_TOP[rpu_r5{0:1}_reset]

RPU MPCore resets.

Entire RPU power island.

AXI interconnect.

Core resets.

OCM

RST_LPD_TOP[ocm_reset]

OCM memory.

PL-LPD interface

RST_LPD_TOP[s_axi_lpd_reset]

Resets from LPD to PL fabric.

FPD System Elements (CRF_APB Register Set except where noted)

PCIe

RST_FPD_TOP[pcie_cfg_reset]

RST_FPD_TOP[pcie_bridge_reset]

RST_FPD_TOP[pcie_ctrl_reset]

PCIe controller:

Configuration reset.

Bridge reset (AXI interface).

Controller reset.

DisplayPort

RST_FPD_TOP[dp_reset]

DisplayPort controller.

FPD SWDT

RST_FPD_TOP[swdt_reset]

FPD watchdog timer (wdt0).

FPD DMA

RST_FPD_TOP[fpd_dma_reset]

FPD DMA controller.

SATA

RST_FPD_TOP[sata_reset]

SATA controller.

PS-GTR

RST_FPD_TOP[gt_reset]

PS GTR transceivers.

GPU

RST_FPD_TOP[gpu_pp{0:1}_reset]

GPU pixel processors.

HP ports

RST_FPD_TOP[s_axi_hp{0:3}_fpd_reset]

RST_FPD_TOP[s_axi_hpc{0:1}_fpd_reset

PS to PL AXI interfaces.

Cortex-A53 CPU

RST_FPD_APU[acpu{0:3}_pwron_reset]

Individual resets to each APU core.

APU L2 cache reset

RST_FPD_APU[apu_l2_reset]

L2 cache reset.

DDR

PMU_GLOBAL.GLOBAL_RESET [FPD_RST]

The DDR controller can only be successfully reset using the FPD reset.

APM

RST_DDR_SS[apm_reset]

AXI performance monitors on DDR interface ports.