System to Card Flow (Host memory to EP)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Software sets up the SRC-Q with a buffer address in the host and an appropriate buffer size in host memory.

2.Software sets up the DST-Q with a buffer address in the AXI domain and an appropriate buffer size in host memory.

3.Software sets up the STAS-Q and STAD-Q in host memory.

4.On enabling the DMA, the DMA fetches SRC and DST elements over PCIe.

5.The DMA fetches the buffer pointed to by SRC elements (upstream memory read) and provides it on the AXI interface (as AXI write transaction) targeting the AXI address provided in DST-Q.

6.On completion of DMA transfer (encountering EOP), STAS-Q and STAD-Q are updated in host memory.