1.The host software sets up and manages SRC and STAS Q elements in host memory; Arm software (driver on the Zynq UltraScale+ MPSoC) sets up and manages DST and STAD Q elements in AXI memory.
2.The source buffer lies in PCIe memory and destination buffer in AXI memory.
3.DMA channel's registers are programmed by both host CPU and AXI CPU (registers corresponding to SRC/STAS Qs by host and DST/STAD Qs by AXI CPU).
4.On DMA channel enable, the SRC elements are fetched over PCIe and DST elements over AXI.
5.Source buffer pointed by SRC-Q is fetched over PCIe and made available (AXI write transaction on AXI master port) to the destination address (provided by DST-Q) on AXI.
6.On completion of the operation the STAS-Q is updated in host memory and the STAD-Q is updated in AXI memory.