TLB Maintenance Operations

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

SMMU TLB maintenance operations (for example, TLB invalidates) can be initiated in one of the two ways.

Accessing SMMU memory-mapped registers.

Broadcasting TLB maintenance operations to the SMMU through the distributed virtual memory (DVM) bus. Clearing TLB entries through broadcast messages can significantly improve system performance by freeing-up TLB entries. TLB maintenance-message broadcasting is an important feature of the SMMU architecture.