The trace memory controller (TMC) provides on-chip storage and buffering of trace data using RAMs. When configured as an embedded trace FIFO (ETF), the TMC functions as a FIFO to absorb bursts of traces, with the attached RAMs as the FIFO memory. When configured as an embedded trace router (ETR), the TMC can route the trace data into the PS interconnect, through an AXI bus, eventually reaching a large memory pool like external DDR or internal OCM.
There are two ETFs, one in the APU and the other one in the full-power domain. The reason for using an ETF in the APU is to absorb bursts of trace packets from the four CPUs, after they are combined and after the funnel in the APU.
There is one ETR, placed on one replicator output.