TTC Block Diagram

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This Figure is a block diagram of the TTC. The clock-in and wave-out multiplexing for the timer/clock 0 is controlled by the slcr.MIO_PIN_xx registers. If no selection is made in these registers, then the default becomes the EMIO interface.

Figure 14-2:      TTC Block Diagram

X-Ref Target - Figure 14-2

X17918-triple-counter-timer-block.jpg