TTC Programming

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The programming steps for the TTC are listed in Table: TTC Initialization through Table: TTC Stop Timer. This Figure shows the TTC flowchart.

Table 14-6:      TTC Initialization

Task

Register

Register Field

Register Offset

Bits

Value

Check if timer counter is started

counter_control

DIS

0x0C

0

Read operation

Ensure timer counter has not started

Write reset value to the counter control register

counter_control

All

0x0C

31:0

0x21 (hex)

Reset clock control

clock_control

All

0x00

31:0

0x00 (hex)

Reset interval count value

interval_counter

All

0x24

31:0

0x00 (hex)

Reset match-1 value

match_1_counter

All

0x3C

31:0

0x00 (hex)

Reset match-2 value

match_2_counter

All

0x48

31:0

0x00 (hex)

Reset IER

interrupt_enable

All

0x60

31:0

0x00 (hex)

Reset ISR

interrupt_register

All

0x54

31:0

0x00 (hex)

Reset counter

counter_control

RST

0x0C

4

1b'1

Table 14-7:      TTC Set Options

Task

Register

Register Field

Register Offset

Bits

Value

External clock set option

clock_control

C_Src

0x00

5

1b'1

External clock deselect option

clock_control

C_Src

0x00

5

1b'0

Negative edge clock selection

clock_control

Ex_E

0x00

6

1b'1

Negative edge clock deselect

clock_control

Ex_E

0x00

6

1b'0

Interval mode select

counter_control

INT

0x0C

1

1b'1

Interval mode deselect

counter_control

INT

0x0C

1

1b'0

Decrement counter

counter_control

DEC

0x0C

2

1b'1

Decrement counter deselect

counter_control

DEC

0x0C

2

1b'0

Select match mode

counter_control

Match

0x0C

3

1b'1

Deselect match mode

counter_control

Match

0x0C

3

1b'0

Disable waveform output

counter_control

Wave_en

0x0C

5

1b'1

Enable waveform output

counter_control

Wave_en

0x0C

5

1b'0

Select waveform polarity

counter_control

Wave_pol

0x0C

6

1b'0

Select waveform polarity

counter_control

Wave_pol

0x0C

6

1b'0

Table 14-8:      TTC Set Prescaler

Task

Register

Register Field

Register Offset

Bits

Value

Clear prescaler control bits

clock_control

PS_V | PS_En

0x00

4:0

5b'00000

Write the value only if prescaler value is less than 16

clock_control

PS_V | PS_En

0x00

4:0

Prescaler value to
be written

Table 14-9:      Setup Timer

Task

Register

Register Field

Register Offset

Bits

Value

Stop timer

counter_control

DIS

0x0C

0

1b'1

Initialize the device. Refer to TTC Initialization.

Set required options. Refer to TTC Set Options.

Calculate interval and prescaler.

Setup interval

interval_counter

All

0x24

31:0

Interval value calculated in previous step

Set prescaler value calculated in previous step. Refer to TTC Set Prescaler.

Table 14-10:      Setup Ticker

Task

Register

Register Field

Register Offset

Bits

Value

Setup timer. Refer to Setup Timer.

Register the ticker handler with the GIC.

Enable TTC interrupts in the GIC.

Enable interval interrupt

interval_counter

Interval

0x60

0

1b'1

Start timer

counter_control

DIS

0x0C

0

1b'0

Table 14-11:      TTC Stop Timer

Task

Register

Register Field

Register Offset

Bits

Value

Stop timer

counter_control

DIS

0x0C

0

1b'1