TX Buffers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Frames to transmit are stored in one or more transmit AXI buffers. Zero length AXI buffers are allowed and the maximum number of buffers permitted for each transmit frame is 128.

The number of words in each buffer descriptor depends on the operating mode. The first two words (word 0 and word 1) are used for all buffer descriptor modes. In extended buffer descriptor mode, two buffer descriptor words are added for 64-bit addressing mode and two buffer descriptor words are added for timestamp capture. Therefore, there are either two, four, or six buffer descriptor words in each buffer descriptor entry depending on operating mode, and every buffer descriptor entry has the same number of words.

Every descriptor is 64-bits wide when 64-bit addressing is disabled and the descriptor timestamp capture mode is disabled.

Every descriptor is 128-bits wide when 64-bit addressing is enabled and the descriptor timestamp capture mode is disabled.

Every descriptor is 128-bits wide when 64-bit addressing is disabled and the descriptor timestamp capture mode is enabled.

Every descriptor is 196-bits wide when 64-bit addressing is enabled and the descriptor timestamp capture mode is enabled.

To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits [31:0] in the first word of each descriptor list entry.

The second word of the transmit-buffer descriptor is initialized with control information that indicates the length of the frame, whether the MAC is to append CRC, and whether the buffer is the last buffer in the frame.

After transmission, the status bits are written back to the second word of the first buffer along with the used bit. Bit [31] is the used bit that, if transmission is to take place, must be zero when the control word is read. It is written to one once the frame is transmitted. Bits [29:20] indicate various transmit error conditions. Bit [30] is the wrap bit, which can be set for any buffer within a frame. When no wrap bit is encountered, the queue pointer continues to increment.

The transmit-buffer queue base address register can only be updated while transmission is disabled or halted; otherwise any attempted write is ignored. When transmission is halted, the transmit-buffer queue pointer maintains its value. Therefore, when transmission is restarted the next descriptor read from the queue is from immediately after the last successfully transmitted frame. While transmit is disabled, bit [3] of the network control is set Low, the transmit-buffer queue pointer resets to point to the address indicated by the transmit-buffer queue base address register. Disabling receive does not have the same effect on the receive-buffer queue pointer.

When the transmit queue is initialized, transmit is activated by writing a 1 to the transmit start bit [9] of the network control register. Transmit is halted when the used bit of the buffer descriptor is read, a transmit error occurs, or by writing to the transmit halt bit of the network control register.

Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register. Rewriting the start bit while transmission is active is allowed. This is implemented with a transmit_go variable, which is read from the transmit status register at bit [3].

The transmit_go variable is reset when the following occurs.

Transmit is disabled.

A buffer descriptor’s ownership bit set is read.

Bit [10], tx_halt_pclk, of the network control register is written.

There is a transmit error due to too many retries, late collision (gigabit mode only), or a transmit under-run.

To set transmit_go, write to bit [9], tx_start_pclk of the network control register.

Transmit halt does not take effect until any ongoing transmit finishes.

The entire contents of the frame are read into the transmit packet buffer memory, any retry attempt is replayed directly from the packet buffer memory rather than re-fetching it through the AXI.

If a used bit is read mid-way through transmission of a multi-buffer frame, the bit is treated as a transmit error. Transmission stops, tx_er is asserted, and the FCS is bad.

If transmission stops due to a transmit error or a used bit being read, transmission is restarted from the first buffer descriptor of the frame being transmitted when the transmit start bit is rewritten.

Table: TX Buffer Descriptor Entry includes details of the transmit buffer descriptor list.

Table 34-8:      TX Buffer Descriptor Entry

Bit

Function

Word 0

31:0

Byte address of buffer.

Word 1

31

Used: Must be zero for the controller to read data to the transmit buffer. Once it is successfully transmitted, the controller sets this bit to one for the first buffer of a frame. Software must clear this bit before the buffer can be used again.

30

Wrap: Marks the last descriptor in the transmit buffer descriptor list. This can be set for any buffer within the frame.

29

Retry limit exceeded, transmit error detected.

28

Always set to 0.

27

Transmit frame corruption due to AXI error: Set if an error occurs midway while reading through the transmit frame from the AXI, including RESP errors, and buffers exhausted mid-frame. If the buffers run out during transmission of a frame, then transmission stops, the FCS is incorrect, and tx_er is asserted.

26

Late collision, transmit error detected. Late collisions force this status bit to be set in gigabit mode.

25:24

Reserved.

23

For extended buffer descriptor mode. This bit indicates a timestamp is captured in the buffer descriptor. Otherwise the bit is reserved.

22:20

Transmit IP/TCP/UDP checksum generation offload errors:

000b: No error.

001b: The packet is identified as a VLAN type, but the header is not fully complete, or has an error in it.

010b: The packet is identified as a SNAP type, but the header is not fully complete, or has an error in it.

011b: The packet is not of an IP type, or the IP packet was invalidly short, or the IP is not of type IPv4/IPv6.

100b: The packet is not identified as VLAN, SNAP, or IP.

101b: Non-supported packet fragmentation occurred. For IPv4 packets, the IP checksum is generated and inserted.

110b: Packet type detected is not TCP or UDP. TCP/UDP checksum is therefore not generated. For IPv4 packets, the IP checksum is generated and inserted.

111b: A premature end of packet is detected and the TCP/UDP checksum cannot be generated.

19:17

Reserved.

16

No CRC to be appended by the MAC. When set this bit implies that the data in the buffers already contains a valid CRC and no CRC or padding is appended to the current frame by the MAC.

This control bit must be set for the first buffer in a frame and is ignored for the subsequent buffers of a frame. This bit must be clear when using the transmit IP/TCP/UDP checksum generation offload, otherwise checksum generation and substitution does not occur.

15

Last buffer, this bit (when set) indicates that the last buffer in the current frame is reached.

14

Reserved.

13:0

Length of buffer.

Table: TX Descriptor Words: 64-bit Addressing Mode identifies the added descriptor words used when the 64-bit addressing mode is enabled.

Table 34-9:      TX Descriptor Words: 64-bit Addressing Mode

Bit

Function

Word 2 (64-bit Addressing)

31:0

Upper 32-bit address of the data buffer.

Word 3 (64-bit Addressing)

31:0

Unused

Table: TX Descriptor Words: Descriptor Timestamp Capture Mode identifies the added descriptor words used when the descriptor timestamp capture mode is enabled.

Table 34-10:      TX Descriptor Words: Descriptor Timestamp Capture Mode

Bit

Function

Word 2 (32-bit Addressing) or Word 4 (64-bit Addressing)

31:30

Timestamp seconds [1:0]

29:0

Timestamp nanoseconds [29:0]

Word 3 (32-bit Addressing) or Word 5 (64-bit Addressing)

31:4

Unused

3:0

Timestamp seconds [5:2]