TX Queue Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Create two separate TX buffer description lists, one for each TX Q. The process for this setup remains the same for TX Q0 and TX Q1.

2.Program the TX queue pointer registers transmit_q_ptr and transmit_q1_ptr registers with start of respective buffer descriptor lists. The TX MSB address bits remain common for both queues.

3.Enable transmission and queue data to the desired queue via its buffer descriptor list. SW can queue a packet to either Q0 or Q1 based on the application and priority.

4.Both queues can be initialized and used. If not in use, a queue can be terminated using a dummy buffer descriptor where WRAP and USED bit are set.