TXCLK Delay Unit

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The CMD and DAT outputs need to be delayed with regard to the output SD_CLK signal to meet the hold time requirements in various modes of operation. The outgoing SD clock is delayed. The delayed clock is used to flip-flop the CMD/DAT lines and this output is used to drive the SD interface. The SD_CLK output itself is not delayed.