Threshold Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2023-12-21
Revision
2.4 English
Table 17-6:      Threshold Registers

Bit Field Name

Description

RD_LPR_THRSLD

Read LPR threshold.

RD_HPR_THRSLD

Read HPR threshold.

WR_THRSLD

Write threshold.

When the DDRC CAM levels reaches their threshold, the QoS controller applies the following throttling rules.

Table 17-7:      Throttling Rules

Rule

Description

Read channel throttle rules

If ((slots available in read LPR CAM £ read LPR threshold) && PORTn_LPR_CTRL == 1),
then assert pa_rmark to DDRC for all best effort ports.

If ((slots available in read HPR CAM £ read HPR threshold) && PORTn_HPR_CTRL == 1),
then assert pa_rmark to DDRC for all low-latency ports

Write channel throttle rule

If ((slots available in write CAM £ write CAM threshold) && PORTn_WR_CTRL == 1),
then assert pa_wmask to DDRC for all best-effort ports.