Tightly-coupled memories (TCMs) are low-latency memory that provide predictable instruction execution and predictable data load/store timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory banks on the ATCM and BTCM ports, for a total of 128 KB of memory. The division of the RAMs into two banks, and placing them on ports A and B, allows concurrent accesses to both banks by the load-store, instruction prefetch, or AXI slave ports.
The BTCM memory bank is divided into two 32 KB ranks that are connected to the BTCM-0 and BTCM-1 ports of the Cortex-R5F processors. There are two TCM interfaces that permit connection to configurable memory blocks of tightly-coupled memory (ATCM and BTCM).
•An ATCM typically holds interrupt or exception code that must be accessed at high speed, without any potential delay resulting from a cache miss.
•A BTCM typically holds a block of data for intensive processing, such as audio or video processing.
The block diagram of RPU along with the TCMs is shown in This Figure.
The entire 256 KB of TCM can be accessed by R5_0 (in lock-step mode). The PMU block controls power gating to each of the 64 KB TCM banks, through the system power and configuration state (SPCS) registers.