Tightly Coupled Memory Address Map

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

TCMs are mapped in the local address space of each Cortex-R5F processor, but they are also mapped in the global address space for access from any master. The address maps from the RPU point of view and from the global address space are shown in Table: TCM Address Map.

Table 4-5:      TCM Address Map

 

R5_0 View
(Start Address)

R5_1 View
(Start Address)

Global Address View (Start Address)

Split mode

R5_0 ATCM (64 KB)

0x0000_0000

N/A

0xFFE0_0000

R5_0 BTCM (64 KB)

0x0002_0000

N/A

0xFFE2_0000

R5_0 instruction cache (32 KB)

I-Cache

N/A

0xFFE4_0000

R5_0 data cache (32 KB)

D-Cache

N/A

0xFFE5_0000

R5_1 ATCM (64KB)

N/A

0x0000_0000

0xFFE9_0000

R5_1 BTCM (64KB)

N/A

0x0002_0000

0xFFEB_0000

R5_1 instruction cache (32 KB)

N/A

I-Cache

0xFFEC_0000

R5_1 data cache (32 KB)

N/A

D-Cache

0xFFED_0000

Lock-step mode

R5_0 ATCM (128KB)

0x0000_0000

N/A

0xFFE0_0000

R5_0 BTCM (128KB)

0x0002_0000

N/A

0xFFE2_0000

R5_0 instruction cache (32 KB)

I-Cache

N/A

0xFFE4_0000

R5_0 data cache (32 KB)

D-Cache

N/A

0xFFE5_0000

R5_1 slave port is not accessible in lock-step mode.