Time Quanta Clock

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The time quanta clock (TQ_CLK) is derived from the controller reference clock (CAN_REF_CLK) divided by the baud rate prescaler (BRP).

tTQ_CLK = tCAN_REF_CLK * (can.BRPR[BRP] + 1) freqTQ_CLK 
= freqCAN_REF_CLK / (can.BRPR[BRP] + 1)

tSYNC_SEGMENT = 1 * tTQ_CLK tTIME_SEGMENT1 
= tTQ_CLK * (can.BPR[TS1] + 1) tTIME_SEGMENT2 
= tTQ_CLK * (can.BPR[TS2] + 1) tBIT_RATE 
= tSYNC_SEGMENT + tTIME_SEGMENT1 + tTIME_SEGMENT2 freqBIT_RATE 
= freqCAN_REF_CLK / ((can.BRPR[BRP] + 1) * (3 + can.BTR[TS1] + can.BTR[TS2]))

 

TIP:   A given bit-rate can be achieved with several bit-time configurations, but values should be selected after careful consideration of oscillator tolerances and CAN propagation delays. For more information on CAN bit-time register settings, refer to the CAN 2.0A, CAN 2.0B, and ISO 11898-1 specifications.