To change the PS-GTR link rate dynamically (Table: PS-GTR Link Rate):

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Disable the transmitter.

TRANSMITTER_ENABLE = 0x00

2.Set DisplayPort clock speed.

PHY_CLOCK_SELECT = desired link speed

3.Wait for the PHY rate change done and PLL lock.

a.PHY_STATUS bits [3:0] = 4'b1111 (for two lanes) or PHY_STATUS bits [3:0] = 4'b0101 (for one lane)

b.PHY_STATUS bits [4] = 1'b1

4.Enable the transmitter.

TRANSMITTER_ENABLE = 0x01

Table 33-16:      PS-GTR Link Rate

Task

Register

Register Field

Register Offset

Bits

Value

Disable transmitter.

DP_TRANSMITTER_ENABLE

TX_EN

0x0080

0

1b'0

Set DisplayPort clock.

DP_PHY_CLOCK_SELECT

SEL

0x0234

2:0

0x05 = 5.40 Gb/s link

0x03 = 2.70 Gb/s link

0x01 = 1.62 Gb/s link

Wait for the PHY rate change done and PLL lock by checking DP_PHY_STATUS register.

Check reset done.

DP_PHY_STATUS

RESET_LANES_0_1

0x0280

3:0

4'b1111 (for 2 lanes)

4'b0101 (for 1 lane)

Check PLL locked.

DP_PHY_STATUS

RESET_LANES_0_1

0x0280

4

1b'1 indicates PLL has been locked.

Enable transmitter.

DP_TRANSMITTER_ENABLE

TX_EN

0x0080

0

1b'1

Note:   If the current PS-GTR rate is 1.62 Gb/s and you try to set it again to 1.62 Gb/s, the DP.DP_PHY_STATUS [RATE_CHANGE_DONE_0_1] bits will not be set. The PS-GTR reset doesn’t need to be explicitly issued from the software during a dynamic link rate change, it is handled inside the PS-GTR. Therefore, unless the phy configuration changes the link rate from existing value to the desired value, the RATE_CHANGE_DONE_0_1bits won’t be set.