Each DMA channel maintains a counter that provides status information about the number of bytes transferred to a destination. This counter is updated only when a DMA channel receives a BRESP write transaction. This counter always indicates the correct counter (even under an AXI error condition). This counter value is reflected on the APB register. The total transferred byte counter can be cleared by software by writing to the total transferred byte register.
In the case where the total transferred byte count overflows, a DMA channel indicates this as an interrupt. This is non-fatal error and does not affect the functionality of the DMA channel.