Traffic Classes

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Zynq UltraScale+ MPSoC broadly defines three types of traffic classes.

Video/isochronous traffic class is a real-time, fixed bandwidth, fixed maximum latency class. Typically, a long latency and low priority is acceptable, but the latency must be bounded in all cases and never exceed a predefined maximum value.

Low latency (LL) traffic class is a low-latency, high-priority (HPR) class. It is typically assigned the highest memory access priority and can only be surpassed by a video class transaction that has exceeded its threshold maximum latency.

Best effort (BE) traffic is a high-latency, low-priority (LPR) class used for all other traffic types. This class of traffic is typically assigned the lowest memory access priority.

DDR reads are prioritized in one of these three classes: best effort (BER), video/isochronous (VPR), and low latency (LL). DDR writes are prioritized in one of these two classes: best effort (BEW) and video/isochronous (VPW).

Further details are described in the Read and Write Priorities section of this chapter.

The QoS controller ensures that there is space available in the DDR controller content addressable memory (CAM) for video class traffic at all times. It achieves this by continuously monitoring the CAM levels and throttling the XPI data port arbiter requests for non-video class traffic when preprogrammed CAM thresholds are exceeded. When the CAM level drops below the predefined threshold value, it sends a control signal to the DDRC to throttle down all BE requests. When the CAM reaches a programmed threshold level, the QoS controller masks the corresponding AXI port/direction from requesting to the port arbiter (PA) inside the DDRC using the pa_rmask and pa_wmask signals. This Figure shows the functional block diagram of the QoS controller.

Figure 17-3:      QoS Controller Functional Block Diagram

X-Ref Target - Figure 17-3

X15349.jpg

The QoS controller has a defined set of software-programmable registers per port.