Traffic Quality of Service

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In general, traffic can be categorized into three traffic classes based on the quality of service (QoS) value.

High priority (low latency).

Isochronous (regular, time sensitive, e.g., audio and video traffic).

Best effort (bulk transfers).

The low-latency traffic class is primarily intended for CPU (or CPU like) latency critical traffic, and is not recommended for use by transfers with an AXI interface that includes a FIFO.

On each of the FIFO-enabled AXI interfaces, a traffic shaper (QoS controller) is implemented that can be configured to shape the traffic. The S_AXI_HP{0:3}_FPD interfaces are designed to provide a latency guarantee for DDR memory controller accesses. Details on traffic categorization are described in DDR Memory Controller. For details on system-level QoS, refer to PS Interconnect.

 

IMPORTANT:   The [WR_RELEASE_MODE] bit in the AFIFM.WRCTRL register controls the write command release mode. For example, when 1, a write command is released as available and when 0, the data is buffered into the FIFO and a command is released when either 16-beats are enqueued or there is a WLAST (whichever occurs first). When this bit is set to 1, ensure that any masters issuing write transactions do not provide a command without data. Issuing a command without data can lead to starvation and other system-level issues. In other words, before the [WR_RELEASE_MODE] bit is set to 1, choose masters that will only issue write transactions after data is present.