Training Pattern 1 Procedure (Clock Recovery)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Turn off scrambling and set training pattern 1 in the source through direct register writes. See Table: Clock Recovery.

°SCRAMBLING_DISABLE = 0x01

°TRAINING_PATTERN_SET = 0x01

2.Turn off scrambling and set training pattern 1 in the sink DPCD (0x001020x00106) through the AUX channel.

3.Wait 100 µs before reading status registers for all active lanes (0x002020x00203) through the AUX channel.

4.If clock recovery failed, check for voltage swing or pre-emphasis level increase requests (0x002060x00207) and react accordingly. Run this loop up to five times. If after five iterations this has not succeeded, reduce the link speed, if at a high speed and try again. If already at a low speed, training fails.

Table 33-18:      Clock Recovery

Task

Register

Register Field

Register Offset

Bits

Value

Scrambling disable.

DP_SCRAMBLING_DISABLE

SCR_DIS

0x014

0

1b'1

To force training pattern.

DP_TRAINING_PATTERN_SET

TP_SET

0x00C

1:0

00 = Training off.

01 = Training pattern 1, used for clock recovery.

10 = Training pattern 2, used for channel equalization.

11 = Training pattern 3, used for channel equalization for controllers with DisplayPort v1.2.