Training Pattern 2 Procedure (Symbol Recovery, Interlane Alignment)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Turn off scrambling and set training pattern 2 in the source through direct register writes. See Table: Symbol Recovery, Interlane Alignment.

°SCRAMBLING_DISABLE = 0x01

°TRAINING_PATTERN_SET = 0x02

2.Turn off scrambling and set training pattern 2 in the sink DPCD (0x001020x00106) through the AUX channel.

3.Wait 400 µs and then read status registers for all active lanes (0x002020x00203) through the AUX channel.

4.Check the channel equalization, symbol lock, and interlane alignment status bits for all active lanes (0x00204) through the AUX channel.

5.If any of these bits are not set, check for voltage swing or pre-emphasis level increase requests (0x002060x00207) and react accordingly.

6.Run this loop up to five times. If after five iterations this has not succeeded, reduce the link speed if at a high speed and return to the instructions for training pattern 1. If already at a low speed, training fails.

7.Signal the end of training by enabling scrambling and setting training pattern to 0x00 in the sink device (0x00102) through the AUX channel.

8.On the source side, re-enable scrambling and turn off training.

°TRAINING_PATTERN_SET = 0x00

°SCRAMBLING_DISABLE = 0x00

At this point, training has completed.

Note:   Training pattern 3 replaces training pattern 2 for 5.4 G link rate devices. See the DisplayPort v1.2 specification for details.

Table 33-19:      Symbol Recovery, Interlane Alignment

Task

Register

Register Field

Register Offset

Bits

Value

Scrambling disable

DP_SCRAMBLING_DISABLE

SCR_DIS

0x014

0

1b'1

To force training pattern

DP_TRAINING_PATTERN_SET

TP_SET

0x00C

1:0

00 = Training off.

01 = Training pattern 1, used for clock recovery.

10 = Training pattern 2, used for channel equalization.

11 = Training pattern 3, used for channel equalization for controllers with DisplayPort v1.2.