Transmit Buffer Descriptor List

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The data to be transmitted is read from buffers present in system memory. These buffers are listed in the transmit buffer queue. Refer to DMA Controller and Table: RX Buffer Descriptor Entry for more information on implementation and structure of the TX buffer descriptor. The transmit buffer queue pointer registers (gem.transmit_q{ , 1}_ptr) points to this data structure.

To create a list of buffer descriptors with N entries:

1.Each buffer descriptor is 8 bytes in length. Allocate an area of 8N bytes for the transmit buffer descriptor list in system memory which creates N entries in this list. It is advisable to use un-cached memory for allocating the complete buffer descriptor list for the reasons already described for the Receive Buffer Descriptor List.

2.Mark all entries in this list as owned by the controller. Set bit [31] of word [1] to 0.

3.Mark the last descriptor in the list with the wrap bit. Set bit [30] in word [1] to 1.

4.Write the base address of transmit buffer descriptor list to Controller registers gem.transmit_q{ , 1}_ptr.

Note:   See the Q pointer note under Initialize the Controller.