Transport Layer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The function of the SATA transport layer is to interface between the command and link layers in the transmission and reception of the frame information structures (FIS).

On transmit, the transport layer frames the FIS placed into the TX FIFO. The FISs are framed based on a programmed length for non-data FIS and or a configurable length for data FIS. When the transport layer is instructed to send a non-data FIS, it employs a retry policy until the far end signals acceptance of the transmitted FIS.

On reception, the transport layer de-frames the FIS and places them into the RX FIFO. When a FIS is received, the transport layer informs the command layer.

For a non-data FIS the FIS is considered received when the EOF is signaled by the link layer and the FIS is received with a good CRC.

For a short vendor-specific FIS, the FIS is considered as a non-data FIS. For longer vendor-specific FIS, the FIS reception is signaled when the RX FIFO reaches its watermark.

For a data FIS, the FIS is considered received when the first double word (header) is written into the FIFO.

The transport layer is responsible for crossing the clock domain between the transport layer txDouble word and rxDouble word clocks and command layer clock domain. The receive FIFO is written to on the transport layer receive double-word clock with data contained in the FIS sent by the link layer. Once the data is stable at the output of the receive FIFO, on the command layer clock domain, the command layer can take the data. If the command layer is not ready to accept the data, the data builds up in the receive FIFO. When the receive FIFO exceeds its threshold, the transport layer stalls the link layer, which sends HOLD primitives to the far end to stall it. This threshold takes into consideration the latency involved in getting the far end to stop transmitting the data. This threshold is programmable to allow for the use of high latency repeaters or re-timers in between the host and device.

The transmit FIFO is written to on the command layer clock, with data to be sent in the FIS transferred by the DMA controller. Once the data is stable at the output of the transmit FIFO on the transmit double word clock domain, the link layer can take the data. If the transmit FIFO cannot supply data to the link layer, the transport layer stalls the link layer, which sends HOLD primitives to the far end to stall it.