Two SPI Flash Memories with Separate Buses (Dual Parallel)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The generic Quad-SPI controller supports up to two SPI flash memories operating in parallel as shown in This Figure. Unlike the legacy Quad-SPI (LQSPI) controller, the chip select is driven independently to the upper and lower flash memory devices. The selection of the lower/upper memory is controlled by using the data bus select field (Table: Generic Quad-SPI Controller: SPI Mode Commands). With this approach, commands and data can be transmitted and received from both devices, or only upper or only lower flash memory device. In this configuration, the device level XIP mode is not supported.

Figure 24-9:      Dual Parallel Mode

X-Ref Target - Figure 24-9

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