Two SPI Flash Memories with a Shared Bus (Stacked)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

To reduce I/O pin count, the generic Quad-SPI controller also supports two SPI flash memories in a shared bus arrangement. This Figure shows an example of a lower data bus connected to both flash devices. It is also possible to connect the upper data bus to both flash devices. The lower or upper memory selection is controlled by the data bus select field.

Figure 24-10:      Stacked Mode

X-Ref Target - Figure 24-10

X15439-qspi-stacked-mode-block.jpg