Type Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR_QOS_CTRL.PORT_TYPE register (2 bits) specifies the traffic class for each of the six ports.

Bit Field Value

Description

00

Best effort traffic class.

01

Low-latency traffic class.

10

Video/isochronous traffic class.

11

Reserved