UART Controller Programming

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The programming steps/tasks for the UART controller are listed in Table: UART Configuration through Table: UART Receive Data.

UART Configuration

UART Self Test

UART Set Operating Mode

UART Send Data

UART Receive Data

Table 21-5:      UART Configuration

Task

Register

Register Field

Register Offset

Bits

Note

Set the default baud rate 115200 b/s.

Fastest possible input clock data rate is 25 MHz/2, ensure requested data rate does not exceed the limit.

Read bit 0 in mode register (base + 0x04) to check if clock/8 option is set.

Check if input clock is divided by 8.

Mode register

Clk_sel

0x004

0

Read operation

If clk_sel bit is set, divide input clock value by 8 to calculate baud rate.

Calculate baud rate generator value (Best_BRGR).

Calculate baud rate divider value (Best_BAUDDIV).

Disable UART

Configuration register

RX_DIS | TX_DIS

0x000

5 and 3

28h

Clear bit 5:2 in base + 0x00.

Set bit 5 and bit 3 in base + 0x00.

Write baud rate generator value

Baud generator register

All

0x018

31:0

Best_BRGR

Write baud rate divider value

Baud divider register

All

0x0034

31:0

Best_BAUDDIV

Reset TX and RX

Configuration register

TX_RST | RX_RST

0x00

1:0

11b

Enable UART

Configuration register

RX_DIS | TX_DIS

0x000

5 and 3

0

Clear bit 5:2 in base + 0x00.

Set bit 2 and bit 4 in base + 0x00.

Clear bits 1, 2, 3, 4, 5, and 7 in base + 0x04. Set bit 5 in base + 0x04.

Set mode to 8-bit, 1 stop, and no parity

Mode register

CHAR_LEN_8BIT | PARITY_NONE | STOPMODE_1

0X004

7, 5:1

Reg = 20h

Write value to set RXFIFO trigger 8 bytes.

RX_WM

All

0x0020

31:0

8h

Write RX time-out value.

Timeout register

All

0x001C

31:0

1h

Write values to disable all interrupts.

Interrupt disable

All

0x00C

12:0

1FFFh

Table 21-6:      UART Self Test

Task

Register

Register Field

Register Offset

Bits

Note

Save interrupt mask register contents.

Interrupt mask register

All

0x0010

31:0

Read operation

Disable all interrupts.

Interrupt disable

All

0x00C

12:0

1FFFh

Save mode register contents.

Mode register

All

0x004

31:0

Read operation

Enable local loopback.

Mode register

CH_mode L_LOOP

0x004

9:8

10b

Sending data refer section UART send data.

Wait until RXFIFO empty flag cleared

Status register

RX_EMPTY

0x02c

2

Read and check

Wait until RXFIFO empty flag is set.

Receive data, refer to UART receive data section. Repeat previous three steps until all bytes (sent and received) are transferred.

Verify all data received (both send and receive buffers).

Restore (write back) interrupt mask value saved in first step.

Interrupt enable register

All

0x008

31:0

Value read in the first task of this UART self-test procedure.

Restore mode register contents.

Mode register

All

0x004

31:0

Value read in the third task of this UART self-test procedure.

Table 21-7:      UART Set Operating Mode

Task

Register

Register Field

Register Offset

Bits

Note

Clear bits 9 and 8 in base + 0x04. Then, set bits 9:8.

For normal mode (0).

Mode register

CHMODE

0x004

9:8

00b

For auto mode (1).

Mode register

CHMODE

0x004

9:8

01b

For local loop back mode (2).

Mode register

CHMODE

0x004

9:8

10b

For remote loop back mode (3).

Mode register

CHMODE

0x004

9:8

11b

Table 21-8:      UART Send Data

Task

Register

Register Field

Register Offset

Bits

Note

Set bits 8 and 7 in base+0x0C to disable interrupts.

Disable interrupts.

Interrupt disable register

TX_EMPTY | TX_FULL

0x0C

4:3

11b

Check bit number 8 in base+0x2C.

Check if TX_FULL bit is set, if TXFIFO is full, send nothing.

Status register

TXFULL

0x02C

4

Read

If TX_FULL is not set, fill the remaining bytes.

TXFIFO register

All

0x0030

31:00

Data to be sent

Perform previous two tasks until all bytes transferred.

Read interrupt mask register

Interrupt mask register

RX_FULL | RX_EMPTY | RX_OVR_FLW

0x0010

2:0

Read

If any of RXFIFO full or RXFIFO empty or RX overflow interrupts are set, enable TX empty interrupt by setting bit 3 in base + 0x008.

If any bit set from previous operation, write TXEMPTY bit to 1.

Interrupt enable register

TX_EMPTY

0x8

3

1b

Wait until the transfer is over by monitoring bit 11 (transfer active) and bit 7 (TX empty) in base + 0x2C.

Table 21-9:      UART Receive Data

Task

Register

Register Field

Register Offset

Bits

Note

Save interrupt mask register (base+0x10) offset contents.

Disable interrupts.

Interrupt disable register

All

0x0C

4:3

1FFFh

Wait until all data received by checking the bit 1 in status register (base+0x002C) to check the RXFIFO is empty.

Check RX_EMPTY flag.

Status register

RX_EMPTY

0x002C

1

Read operation

Receive data by reading FIFO register.

FIFO register

All

0x0030

31:0

Read data operation

Do the previous two operations until RX_EMPTY is not set and bytes yet to be sent.

Restore the interrupt mask register.

Interrupt enable register

All

0x008

31:0

Value read in first step.