USB Controller Features

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Two USB 2.0/3.0 controllers

Supports a 5.0 Gb/s data rate

Supports host and device modes

Supports on-the-go (OTG) host/device selection for USB 2.0 (only)

Provides simultaneous operation of the USB 2.0 and USB 3.0 interfaces (only in host 3.0 mode).

64-bit AXI master port with built-in DMA

AXI port for register programming

Power management features: hibernation mode

Support for 48-bit address space

Supports 12 endpoints (six out and six in)

Note:   When the USB controller is used in a 3.0 configuration, USB 2.0 mode must also be enabled in the MPSoC processor configuration window (PCW). This is necessary because the DC voltage bus (VBUS) valid signal from the ULPI interface PHY is used. Consequently, it is mandatory to enable the USB 2.0 mode though the USB 3.0 mode is required irrespective of the host, device, or OTG modes.