Upon HPD Assertion

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Read the DPCD capabilities fields out of the sink device (0x000000x0000B) through the AUX channel. See Table: HPD Assertion.

2.Determine values for lane count, link speed, enhanced framing mode, downspread control, and main link channel code based on each link partners' capability and needs.

3.Write the configuration parameters to the link configuration field (0x001000x00101) of the DPCD through the AUX channel.

Note:   Some sink devices' DPCD capability fields are unreliable. Many source devices start with the maximum transmitter capabilities and scale back as necessary to find a configuration the sink device can handle. This could be an advisable strategy instead of relying on DPCD values.

4.Equivalently, write the appropriate values to the source controller's local configuration space.

a.LANE_COUNT_SET

b.LINK_BW_SET

c.ENHANCED_FRAME_EN

d.PHY_CLOCK_SELECT

Table 33-17:      HPD Assertion

Task

Register

Register Field

Register Offset

Bits

Value

To set lane count.

DP_LANE_COUNT_SET

LANE_CNT

0x004

4:0

Possible values:

5b'00001

5b'00010

To set the value of the main link bandwidth for the sink device.

DP_LINK_BW_SET

BW

0x000

7:0

0x06 = 1.62 Gb/s

0x0A = 2.7 Gb/s

0x14 = 5.4 Gb/s

To enable enhanced framing.

DP_ENHANCED_FRAME_EN

ENH_FRAMING_EN

0x008

0

Set to 1 by the source to enable the enhanced framing symbol sequence.

Select PHY clock.

DP_PHY_CLOCK_SELECT

SEL

0x0234

2:0

0x05 = 5.40 Gb/s link

0x03 = 2.70 Gb/s link

0x01 = 1.62 Gb/s link