Use Case: Check Success of Page Program/Erase

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When a page program/erase command is issued to a flash device, the software needs to poll the status of the operation. This requires multiple read requests to the status register. By setting the poll bit 1, the generic Quad-SPI controller continuously reads the data and checks the expected status bits. This mechanism avoids having the software/processor issue multiple read requests and is controlled on the MPSoC by the generic Quad-SPI controller.

When the poll bit is set the useful fields are listed.

Generic FIFO field—SPI mode.

Generic FIFO field—receive.

Generic FIFO field—data bus select.

Poll register field—POLL_DATA value.

Poll register field—enable lower data bus mask.

Poll register field—enable upper data bus mask.

Poll register field—data bus mask, the same value is used for both upper and lower devices.

In the case of a polling operation when one data bus of a generic Quad-SPI controller is active, in single mode or stacked mode, only one data bus is active and the value of the data bus select is either 2'b01 or 2'b10. In this case, only one device is connected to the generic Quad-SPI controller. Hence, the data on the connected device is captured and compared against the POLL_DATA field of the poll register.

In the case of a polling operation when two data buses of a generic Quad-SPI controller are active, in dual-parallel mode, there are two devices connected to the generic Quad-SPI controller. When the value of receive = 1'b1, the possible values of the data bus select are 2'b01, 2'b10, or 2'b11.

When receive = 1'b1 and the data bus select is 2'b01, the data in the lower device is captured and compared against the immediate_data field depending on the poll mask register values.

When receive = 1'b1 and the data bus select is 2'b10, the data in the upper device is captured and compared against the POLL_DATA field depending on the poll mask register value.

When receive = 1'b1 and the data bus select is 2'b11, the data in both the lower and upper devices is captured simultaneously and compared independently against the POLL_DATA field of the poll register. The generic Quad-SPI controller reads the data from both data buses. It compares the data against value that is configured in the POLL_DATA field of the poll register, also considering the poll mask value. The controller waits until the data matches. Once the data matches, the controller goes to the next entry (if any) of the generic FIFO.