Use Cases

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section describes how each protection unit is used for this programming example.

XMPU DDR Protection Units: The APU transactions are routed through the CCI and to access the DDR memory via the DDR XMPU{1, 2} protection units. Other system masters can also use this path, but they are blocked by the protection units using AXI Master ID filtering. In this example system, only an APU core is allowed to access the DDR memory controller.

The DDR XMPU{0, 3, 4, 5} units are disabled; the RPU, PL masters, and others are not permitted to access DDR memory.

XMPU FPD Protection Unit: APU transactions are routed through the FPD XMPU protection unit to reach the SATA AHCI memory-mapped registers in the SIOU.

XMPU OCM Protection Unit: RPU transactions are routed through the OCM XMPU protection unit to reach the OCM memory.

XPPU Protection Unit: The XPPU protection unit permits access to the I2C and GEM registers.