Video Clock Example

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

To generate a 296.703 MHz video clock from a 27 MHz source, use the following parameters. The VCO frequency will be 2373.6 MHz and the VPLL clock output will be 1186.8 MHz.

Program the multiplier. Set M = 87.

Program the fractional modulus. Set F = 59775.

Program VPLL to divide by 2. Set CRF_APB.VPLL_CTRL [DIV2] = 1.

Program video clock generator to divide by 4. Set CRF_APB..DP_VIDEO_REF_CTRL [DIVISOR0] = 4.