Video Decoder

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The VCU decoder includes two interconnected HEVC/AVC decoders. It also contains global registers, an interrupt controller, and a timer.

The VCU decoder is controlled by a microcontroller (MCU) subsystem. A 32-bit APB slave interface is used by the system CPU to control the MCU. Two 128-bit AXI4 master interfaces are used to fetch video input data and store video output data from/to the system memory. Two 32-bit AXI4 master interfaces are used to fetch the MCU software (instruction cache interface) and load/store additional MCU data (data cache interface).

Each decoder includes control registers, a bridge unit and a set of internal memories. The bridge unit manages the request arbitration, burst addresses, and burst lengths for all external memory accesses required by the decoder. It also handles format conversion and border extension.

The VCU has a direct access to the system data bus through a high-bandwidth master interface to transfer video data to/from an external memory.

The VCU control software is partitioned into two layers. The application software runs on the RPU or APU MPCores, and the low-level code is implemented in the MCU. The processor communicates with the embedded MCU through a slave interface, which is also connected to the system bus.