Video Timing Generation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When using the live video interface, the video timing signals can be generated internally by using the VTC block in the PS or the video timing generator block in the PL. The VTC block in the PS accepts the PL live video clock (dp_video_in_clk) as an input and can generate HSYNC and VSYNC signals. The VTC accepts clock inputs from two sources.

Live video clock input (dp_video_in_clk) from the PL.

Video clock generated from the video PLL.

When using a live video input from an external interface (for example, an HDMI input), the video timing must be generated in the PL. For a live video output, the VTC block in the PS can be used to generate the video timing signals.

When using the video PLL for generating the reference clock for the DisplayPort controller, the programming flow is the same as the other PS PLLs. The video PLL can accept input from any of the available reference clock inputs (PS_REF_CLK, ALT_REF_CLK, AUX_REF_CLK, or VIDEO_CLK). It requires the helper data (mentioned in PS Clock Subsystem) to program the appropriate values of the PLL attributes.