Wait for Buffer Read Ready Interrupt

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

15.Write a 1 to the buffer read ready in the normal interrupt status register to clear this bit.

16.Read the block data (in accordance with the number of bytes specified in step 1) from the buffer data port register.

17.Repeat until all blocks are received and then go to step 18.

18.If this sequence is for a single or multiple block transfer, go to step 19. For an infinite block transfer, go to step 21.

19.Wait for a transfer complete interrupt.

20.Write a 1 to the transfer complete in the normal interrupt status register to clear this bit.

21.Perform the sequence for abort transaction.

Note:   Step 1 and step 2 can be executed at same time. Step 4 and step 5 can also be executed at same time.

 

IMPORTANT:   During the process of auto tuning, the software driver must ignore the reg_presentstate (SDIO) register’s [sdhcdmactrl_piobufrdena] field before sending CMD19 or CMD21.