Word Detection

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The start of a word is detected in the SPI_REF_CLK clock domain.

Detection when controller is enabled: If the controller is enabled (from a disabled state) at a time when the slave select is active-Low, the controller ignores the data and waits for the SCLK to be inactive (a word boundary) before capturing data. The controller counts SCLK inactivity in the SPI_REF_CLK domain. A new word is assumed when the SCLK idle count reaches the value programmed into the [Slave_Idle_count] bit field.

Detection when slave select is asserted: With the controller enabled and slave select is detected as High (inactive), the controller assumes the start of the word occurs on the next active edge of SCLK after slave select transitions active-Low.

 

IMPORTANT:   The start condition must be held active for at least four SPI_REF_CLK cycles to be detected. If slave mode is enabled at a time when the master is very close to starting a data transfer, there is a small probability that false synchronization will occur, causing packet corruption. This issue is avoided by any of the following design selections.

Ensure that the external master does not initiate data transfer until at least ten SPI_REF_CLK cycles are complete after slave mode is enabled.

Ensure that slave mode is enabled before the master is enabled.

Ensure that the slave select input signal is not active when the slave is enabled.