The write bit deskew algorithm is performed in parallel for all byte lanes and requires write and read access to memory. The goal of the PHY write bit deskew algorithm is to align a 0-to-1 transition on each of the data bits in the write path. An initial pattern is written into memory, read back, and then evaluated. Then per-bit delay lines are used to align all the data bits to each other. After deskewing, another read is executed to confirm data integrity.
Write bit deskew completion is signaled by the PGSR0.WDDONE bit. The high-level error flag is PGSR0.WDERR. Additional debugging information is listed in Table: DATX8 General Status Register (DXnGSR2) and Table: Write Bit Deskew Error Indications.
The results of write bit deskew can viewed in the DXnBDLR0, DXnBDLR1, and DXnBDLR2 registers, as listed in Table: Write Bit Deskew Error Indications.