Write Bit Deskew

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The write bit deskew algorithm is performed in parallel for all byte lanes and requires write and read access to memory. The goal of the PHY write bit deskew algorithm is to align a 0-to-1 transition on each of the data bits in the write path. An initial pattern is written into memory, read back, and then evaluated. Then per-bit delay lines are used to align all the data bits to each other. After deskewing, another read is executed to confirm data integrity.

Write bit deskew completion is signaled by the PGSR0.WDDONE bit. The high-level error flag is PGSR0.WDERR. Additional debugging information is listed in Table: DATX8 General Status Register (DXnGSR2) and Table: Write Bit Deskew Error Indications.

Table 17-21:      DATX8 General Status Register (DXnGSR2)

Register

Bits

Name

Description

Address

DX0GSR2

[2]

WDERR

Write bit deskew error: if set, indicates that the DATX8 has encountered an error during execution of the write bit deskew training of byte 0.

FD0807E8

DX1GSR2

[2]

WDERR

Same as above, for byte 1.

FD0808E8

DX2GSR2

[2]

WDERR

Same as above, for byte 2.

FD0809E8

DX3GSR2

[2]

WDERR

Same as above, for byte 3.

FD080AE8

DX4GSR2

[2]

WDERR

Same as above, for byte 4.

FD080BE8

DX5GSR2

[2]

WDERR

Same as above, for byte 5.

FD080CE8

DX6GSR2

[2]

WDERR

Same as above, for byte 6.

FD080DE8

DX7GSR2

[2]

WDERR

Same as above, for byte 7.

FD080EE8

DX8GSR2

[2]

WDERR

Same as above, for byte 8.

FD080FE8

DX0GSR2

[3]

WDWN

Write bit deskew warning: if set, indicates that the DATX8 has encountered a warning during execution of the write bit deskew training of byte 0.

FD0807E8

DX1GSR2

[3]

WDWN

Same as above, for byte 1.

FD0808E8

DX2GSR2

[3]

WDWN

Same as above, for byte 2.

FD0809E8

DX3GSR2

[3]

WDWN

Same as above, for byte 3.

FD080AE8

DX4GSR2

[3]

WDWN

Same as above, for byte 4.

FD080BE8

DX5GSR2

[3]

WDWN

Same as above, for byte 5.

FD080CE8

DX6GSR2

[3]

WDWN

Same as above, for byte 6.

FD080DE8

DX7GSR2

[3]

WDWN

Same as above, for byte 7.

FD080EE8

DX8GSR2

[3]

WDWN

Same as above, for byte 8.

FD080FE8

DX0GSR2

[11:8]

ESTAT

Error status: If an error occurred for byte 0 as indicated by WDERR, the error status code can provide additional information regarding when the error occurred during the algorithm execution.

FD0807E8

DX1GSR2

[11:8]

ESTAT

Same as above, for byte 1.

FD0808E8

DX2GSR2

[11:8]

ESTAT

Same as above, for byte 2.

FD0809E8

DX3GSR2

[11:8]

ESTAT

Same as above, for byte 3.

FD080AE8

DX4GSR2

[11:8]

ESTAT

Same as above, for byte 4.

FD080BE8

DX5GSR2

[11:8]

ESTAT

Same as above, for byte 5.

FD080CE8

DX6GSR2

[11:8]

ESTAT

Same as above, for byte 6.

FD080DE8

DX7GSR2

[11:8]

ESTAT

Same as above, for byte 7.

FD080EE8

DX8GSR2

[11:8]

ESTAT

Same as above, for byte 8.

FD080FE8

Table 17-22:      Write Bit Deskew Error Indications

PGSR0.WDERR

DXnGSR2.WDERR

DXnGSR2.ESTAT

PGSR0.
WDDONE

Error Condition

1

1

0000

1

Initial write data is skewed by more than three beats of data prior to any deskew.

1

1

0001

1

Write DQS/DQS# is too early relative to data, and during deskew, DQ LCDL is at minimum value and any write DQ BDL is at minimum value.

1

1

0010

1

While searching for left edge of write data eye, DQ LCDL is at the maximum value and any write DQ BDL is at the maximum value.

1

1

1100

1

Read data miscompare after write bit deskew.

The results of write bit deskew can viewed in the DXnBDLR0, DXnBDLR1, and DXnBDLR2 registers, as listed in Table: Write Bit Deskew Error Indications.

Table 17-23:      Write Bit Deskew Error Indications

Register

Bits

Name

Description

Address

DXnBDLR0

[5:0]

DQ0WBD

DQ0 write bit delay: delay select for the BDL on DQ0 write path.

FD080740, FD080840, FD080940, FD080A40, FD080B40, FD080C40, FD080D40, FD080E40, FD080F40

DXnBDLR0

[13:8]

DQ1WBD

DQ1 write bit delay: delay select for the BDL on DQ1 write path.

FD080740, FD080840, FD080940, FD080A40, FD080B40, FD080C40, FD080D40, FD080E40, FD080F40

DXnBDLR0

[21:16]

DQ2WBD

DQ2 write bit delay: delay select for the BDL on DQ2 write path.

FD080740, FD080840, FD080940, FD080A40, FD080B40, FD080C40, FD080D40, FD080E40, FD080F40

DXnBDLR0

[29:24]

DQ3WBD

DQ3 write bit delay: delay select for the BDL on DQ3 write path.

FD080740, FD080840, FD080940, FD080A40, FD080B40, FD080C40, FD080D40, FD080E40, FD080F40

DXnBDLR1

[5:0]

DQ4WBD

DQ4 write bit delay: delay select for the BDL on DQ4 write path.

FD080744, FD080844, FD080944, FD080A44, FD080B44, FD080C44, FD080D44, FD080E44, FD080F44

DXnBDLR1

[13:8]

DQ5WBD

DQ5 write bit delay: delay select for the BDL on DQ5 write path.

FD080744, FD080844, FD080944, FD080A44, FD080B44, FD080C44, FD080D44, FD080E44, FD080F44

DXnBDLR1

[21:16]

DQ6WBD

DQ6 write bit delay: delay select for the BDL on DQ6 write path.

FD080744, FD080844, FD080944, FD080A44, FD080B44, FD080C44, FD080D44, FD080E44, FD080F44

DXnBDLR1

[29:24]

DQ7WBD

DQ7 write bit delay: delay select for the BDL on DQ7 write path.

FD080744, FD080844, FD080944, FD080A44, FD080B44, FD080C44, FD080D44, FD080E44, FD080F44

DXnBDLR2

[5:0]

DMWBD

DM write bit delay: delay select for the BDL on DM write path.

FD080748, FD080848, FD080948, FD080A48, FD080B48, FD080C48, FD080D48, FD080E48, FD080F48