LPDDR4 memory devices use an unmatched DQS-DQ path to enable high-speed performance and save power. As a result, the DQS strobe is trained to arrive at the DQ latch center-aligned with the data eye. The DQ receiver latches the data present on the DQ bus when DQS reaches the latch. DQS2DQ training is accomplished by delaying the DQ signals relative to DQS such that the data eye arrives at the receiver latch centered on the DQS transition. DQS to DQ training is referred to as write training in the JEDEC® standard and write DQ training in the DFI standard.
DQS2DQ training completion is signaled by the PGSR0.DQS2DQDONE bit. If errors are encountered during training, PGSR0.DQS2DQERR is set. Per byte error flags are visible in DXnGSR2.DQS2DQERR, as listed in Table: DQS2DQ Training Error Flags.
Table 17-19: DQS2DQ Training Error Flags
Register
|
Bits
|
Name
|
Description
|
Address
|
DX0GSR2
|
[15:12]
|
DQS2DQERR
|
Write DQS2DQ training error: if set, indicates that the DATX8 has encountered an error during execution of the write DQS2DQ training of byte 0. Each 2 bits indicate an error on one rank. (e.g. bits [13:12] indicate an error on rank 0) Status encoding is: 2'b00: No error 2'b01: oscillator results are all 0s 2'b10: oscillator results are all 1s 1'b11: oscillator results read timeout
|
0xFD0807E8
|
DX1GSR2
|
[15:12]
|
DQS2DQERR
|
Same as above, for byte 1.
|
0xFD0808E8
|
DX2GSR2
|
[15:12]
|
DQS2DQERR
|
Same as above, for byte 2.
|
0xFD0809E8
|
DX3GSR2
|
[15:12]
|
DQS2DQERR
|
Same as above, for byte 3.
|
0xFD080AE8
|
DX8GSR2
|
[15:12]
|
DQS2DQERR
|
Same as above, for ECC byte.
|
0xFD080FE8
|
Additional debugging info is available in the DXnLCDLR1 and DXnGTR0 registers, as listed in Table: Write DQS2DQ Training Debug Registers.
Table 17-20: Write DQS2DQ Training Debug Registers
Register
|
Bits
|
Name
|
Description
|
Address
|
DX0LCDLR1
|
[8:0]
|
WDQD
|
Write data delay: delay select for the write data (WDQ) LCDL for byte 0.
|
0xFD080784
|
DX1LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 1.
|
0xFD080884
|
DX2LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 2.
|
0xFD080984
|
DX3LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for byte 3.
|
0xFD080A84
|
DX8LCDLR1
|
[8:0]
|
WDQD
|
As described above, but for ECC byte.
|
0xFD080F84
|
DX0GTR0
|
[26:24]
|
WDQSL
|
DQ write path latency pipeline for byte 0: Write data is pipelined by (WLSL + WDQSL). Total write data pipeline is: [Write leveling system latency] + WDQSL/2 DRAM clock periods.
|
0xFD0807C0
|
DX1GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 1.
|
0xFD0808C0
|
DX2GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 2.
|
0xFD0809C0
|
DX3GTR0
|
[26:24]
|
WDQSL
|
Same as above, for byte 3.
|
0xFD080AC0
|
DX8GTR0
|
[26:24]
|
WDQSL
|
Same as above, for ECC byte.
|
0xFD080FC0
|