Write Eye Centering

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The write eye centering algorithm is performed in parallel for all byte lanes and requires write and read access to memory. The goal of the PHY write eye centering algorithm is to center the strobe within the data eye in each byte in the write path. An initial pattern is written into memory, read back, and then evaluated. Then write DQ is moved to find the left and right edges of the write eye, and the optimal position is calculated. After centering, another read is executed to confirm data integrity.

Write eye centering completion is signaled by the PGSR0.WEDONE bit. The high-level error flag is PGSR0.WEERR. Additional debugging information is available in DXnGSR2 as listed in Table: DATX8 General Status Register 2 (DXnGSR2) and Table: Write Eye Centering Error Indications.

Table 17-27:      DATX8 General Status Register 2 (DXnGSR2)

Register

Bits

Name

Description

Address

DX0GSR2

[6]

WEERR

Write eye centering error: if set, indicates that the DATX8 has encountered an error during execution of the write eye centering training of byte 0.

FD0807E8

DX1GSR2

[6]

WEERR

Same as above, for byte 1.

FD0808E8

DX2GSR2

[6]

WEERR

Same as above, for byte 2.

FD0809E8

DX3GSR2

[6]

WEERR

Same as above, for byte 3.

FD080AE8

DX4GSR2

[6]

WEERR

Same as above, for byte 4.

FD080BE8

DX5GSR2

[6]

WEERR

Same as above, for byte 5.

FD080CE8

DX6GSR2

[6]

WEERR

Same as above, for byte 6.

FD080DE8

DX7GSR2

[6]

WEERR

Same as above, for byte 7.

FD080EE8

DX8GSR2

[6]

WEERR

Same as above, for byte 8.

FD080FE8

DX0GSR2

[7]

WEWN

Write eye centering warning: if set, indicates that the DATX8 has encountered a warning during execution of the write eye centering training of byte 0.

FD0807E8

DX1GSR2

[7]

WEWN

Same as above, for byte 1.

FD0808E8

DX2GSR2

[7]

WEWN

Same as above, for byte 2.

FD0809E8

DX3GSR2

[7]

WEWN

Same as above, for byte 3.

FD080AE8

DX4GSR2

[7]

WEWN

Same as above, for byte 4.

FD080BE8

DX5GSR2

[7]

WEWN

Same as above, for byte 5.

FD080CE8

DX6GSR2

[7]

WEWN

Same as above, for byte 6.

FD080DE8

DX7GSR2

[7]

WEWN

Same as above, for byte 7.

FD080EE8

DX8GSR2

[7]

WEWN

Same as above, for byte 8.

FD080FE8

DX0GSR2

[11:8]

ESTAT

Error Status: If an error occurred for byte 0 as indicated by WEERR, the error status code can provide additional information on when the error occurred during the algorithm execution.

FD0807E8

DX1GSR2

[11:8]

ESTAT

Same as above, for byte 1.

FD0808E8

DX2GSR2

[11:8]

ESTAT

Same as above, for byte 2.

FD0809E8

DX3GSR2

[11:8]

ESTAT

Same as above, for byte 3.

FD080AE8

DX4GSR2

[11:8]

ESTAT

Same as above, for byte 4.

FD080BE8

DX5GSR2

[11:8]

ESTAT

Same as above, for byte 5.

FD080CE8

DX6GSR2

[11:8]

ESTAT

Same as above, for byte 6.

FD080DE8

DX7GSR2

[11:8]

ESTAT

Same as above, for byte 7.

FD080EE8

DX8GSR2

[11:8]

ESTAT

Same as above, for byte 8.

FD080FE8

Table 17-28:      Write Eye Centering Error Indications

PGSR0.WEERR

DXnGSR2.WEERR

DXnGSR2.ESTAT

PGSR0.
WEDONE

Error Condition

1

1

0000

1

Initial read data miscompare before centering

1

1

0101

1

Read data miscompare after write eye centering.

The results of Write Eye Centering can be viewed in the DXnGTR0 and DXnLCDLR1 registers listed in Table: Write Eye Centering Results Registers.

Table 17-29:      Write Eye Centering Results Registers

Register

Bits

Name

Description

Address

DXnGTR0

[26:24]

WDQSL

DQ write path latency pipeline: Write data is pipelined by (WLSL + WDQSL). Total write data pipeline is:

[Write leveling system latency] + WDQSL/2 DRAM clock periods.

This value is adjusted by LPDDR4 tDQS2DQ training and write eye centering.

Any update in DXnLCDLR1.WDQD updates this field after 20 ctl_clk clock cycles. Reading this field shows the number of pipelines (UI delays) written into the DXnLCDLR1.WDQD field.

Ensure this field is never overwritten by software. Writing into this field changes (corrupts) the total write DQ delay written into the DXnLCDLR1.WDQD field.

FD0807C0, FD0808C0, FD0809C0, FD080AC0, FD080BC0, FD080CC0, FD080DC0, FD080EC0, FD080FC0

 

DXnLCDLR1

[8:0]

WDQD

Write data delay: delay select for the write data (WDQ) LCDL for each byte.

The WDQ LCDL register is automatically updated after DDL calibration (by Tck/4) and after write leveling when write leveling is performed.

Total delay should be written into this field. It overrides the delay set by hardware.

Delay written in this field is converted to following two elements after 20 ctl_clk clock cycles:

1. Number of UI delays (pipelines) added to write dq path that can be read from DxnGTR0.WDQSL field.

2. The remainder of the delay that is the number of LCDL tap delays (written delay - DxnGTR0.WDQSL * one UI period). It is smaller than one UI and is available to read in this field.

Reading this field returns the delay in item 2. This field should be programmed only after running calibration.

FD080784, FD080884, FD080984, FD080A84, FD080B84, FD080C84, FD080D84, FD080E84, FD080F84