After write leveling, the strobe is aligned to the clock at each SDRAM, but it is not known if the strobe is aligned to the correct clock edge. To clear up this ambiguity, a second level of write leveling is used to determine if extra pipeline stages need to be added in the write path due to the write leveling or the board delays.
The write latency adjustment writes a fixed-pattern back-to-back sequence of two BL16s, appended with extra DQS pulses at the end of the last BL16 to obtain a sufficiently long pattern so that nine, previously ambiguous, system write latency situations can be uniquely distinguished. The algorithm writes this data using the minimal DFI pipeline depth.
The distinction is performed by counting the number of one beats in odd and even DQ lines. After determining the write latency, a second sequence of writes and reads are issued to validate the computed latency adjustment setting. For a multi-rank system, this sequence is repeated for each rank.
If an error is detected, the PGSR0.WLAERR field is set. Warnings and errors are flagged in DXnRSR2.WLAWN and DXnRSR3.WLAERR, respectively. See Table: DATX8 Rank Status Registers 2 and 3 (DXnRSR2 and DXnRSR3)
Table 17-21: DATX8 Rank Status Registers 2 and 3 (DXnRSR2 and DXnRSR3)
Register
|
Bits
|
Name
|
Description
|
Address
|
DX0RSR2
|
[1:0]
|
WLAWN
|
Write latency adjustment "DQS off on some DQ lines".
Warning: One bit per rank indicates that, for that rank, the WLA algorithm found some DQ lines where the read data sequence did not match the expected comparison signatures for byte 0.
|
0xFD0807D8
|
DX1RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 1.
|
0xFD0808D8
|
DX2RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 2.
|
0xFD0809D8
|
DX3RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 3.
|
0xFD080AD8
|
DX4RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 4.
|
0xFD080BD8
|
DX5RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 5.
|
0xFD080CD8
|
DX6RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 6.
|
0xFD080DD8
|
DX7RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 7.
|
0xFD080ED8
|
DX8RSR2
|
[1:0]
|
WLAWN
|
Same as above, for byte 8.
|
0xFD080FD8
|
DX0RSR3
|
[1:0]
|
WLAERR
|
Write latency adjustment error: indicates, for each of the system ranks, that an error occurred in the WLA algorithm for byte 0.
|
0xFD0807DC
|
DX1RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 1.
|
0xFD0808DC
|
DX2RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 2.
|
0xFD0809DC
|
DX3RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 3.
|
0xFD080ADC
|
DX4RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 4.
|
0xFD080BDC
|
DX5RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 5.
|
0xFD080CDC
|
DX6RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 6.
|
0xFD080DDC
|
DX7RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 7.
|
0xFD080EDC
|
DX8RSR3
|
[1:0]
|
WLAERR
|
Same as above, for byte 8.
|
0xFD080FDC
|
The write latency adjustment changes the same outputs controlled by write leveling. See Table: Write Leveling Debug Registers for more debugging information.