Write Protect

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The write protect output signal is controlled by the QSPI.GPIO [WP_N] bit. Write protect is often connected on bit [2] of a 4-bit quad-SPI device bus. The write protect signal is driven Low for most flash devices, therefore the reset value is High (write protection deasserted).

In SPI and dual-SPI modes, the write protect signal from the general-purpose I/O register is connected to the WPB pin through the wpn_mo2 output for connection to the write protect control input on the flash device.

In quad mode, the write protect signal is connected as MIO2 and is driven by the controller.

When a write protect operation is not used, the write protect pin is driven to a 1 as expected by the SPI devices. Hence, an internal pull-up resistor is needed by the SPI device.