Write Response Channel

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The write response is generated once the last beat of write data, for a given AXI burst, is accepted by the DDRC. The write response generation makes use of the result of the exclusive access monitor. For a write transaction, the response is always returned as OKAY. For an exclusive write transaction, the response can be returned as OKAY or EXOKAY. A SLVERR response can be returned in the following cases.

Invalid LPDDR3 row address.

On-chip parity address or data error.

Transaction is poisoned.