XMPU Register Set Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each XMPU protection unit is controlled by its own register set. The XMPU registers are listed in Table: XMPU Register Summary. The base addresses for each XMPU is listed in This Figure.

Table 16-8:      XMPU Register Summary

Address

Register Names

Number of Registers

Description

XMPU Control and Status

0x0000

CTRL

1

Default read/write, poison, and alignment configuration.

0x0004+

ERR_STATUS1, ERR_STATUS2

2

Poison address and master ID value (FPD_XMPU), or Poison attribute and base address (DDR_XMPU and OCM_XMPU).

0x000C

POISON

1

Base address of XPPU sink.

0x0010+

ISR, IMR, IEN, IDS

4

Interrupt controls: address decode error, transaction violations.

XMPU Regional Controls

0x0100+

   R{00:15}_START   

16

Region starting base address.

0x0104+      

R{00:15}_END   

16

Region ending base address.

0x0108+   

   R{00:15}_MASTER   

16

   Region master IDs.

0x010C+

   R{00:15}_CONFIG

16

      Region profile: enable, read/write allowed, secure level, relaxed checking.

XMPU Sink for FPD XMPU

0xFD4F_FF00

ERR_STATUS

1

R/W type and offset address access violations.

0xFD4F_FFEC

ERR_CTRL

1

PSLVERR signaling enable.

0xFD4F_FF10+

ISR, IMR, IER, IDR

4

Interrupt controls: register address decode error.