XNandPsu_SetEccAddrSize

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 25-8:      XNandPsu_SetEccAddrSize

Task

Register

Register Field

Register Offset

Bits

Value (Binary)

Calculate and write ECC_Addr, ECC_Size and Slc_Mlc values and program into ECC register.

ECC_Register

All

0x034

27:0

Refer to the register set definitions.

Program BCH mode in memory address register 2.

Memory_Address_Register2

nfc_bch_mode

0x008

27:25

3'b001: 12-bit ECC

3'b010: 8-bit ECC

3'b011: 4-bit ECC

3'b100: 24-bit ECC